It is know to provide data processing systems which sample signal values to form speculative values, the correctness of which are determined at a later time. This allows processing to proceed more rapidly and reduces the amount of margin which needs to be introduced into signal timing so as to cater for worst case performance. An example of such systems are the integrated circuits proposed in WO-A-2004/084072 (embodying an example of so-called Razor techniques).
The above techniques are normally targeted at paths which are slow and performance limiting with the output signal from that path only becoming available close to the required sampling time. Normally, a timing margin is provided to ensure that the correct signal value will be available to be sampled even in worst case operating conditions. The Razor techniques allow this margin to be reduced and yet incorrect operation avoided by sampling the signal value at an aggressively timed point corresponding to the circuit operating at high speed (low voltage, or in accordance with some other performance constraining parameter) and then detecting whether a change in that value being sampled occurs within a subsequent speculation period. If a change does occur, then this is indicative of an incorrect value having been sampled as the speculative value and error recovery operation is triggered.
A problem which can arise in such systems is that a path upon which this type of technique is being used may be critically slow in some circumstances and yet fast in others. When it is fast, then during the speculation period following the speculative sampling the value at the sampling position may validly change due to a new correct value for the following processing cycle propagating through the fast path and reaching the sampling point during the speculation period associated with the previous processing cycle. This behaviour can be considered to correspond to an “race” condition in which the next signal value progresses too rapidly through the processing logic and arrives at the sampling point sufficiently early that it is incorrectly identified as a change in the previous signal value as a consequence of that previous signal value being sampled too early.
One way of dealing with this problem is to insert signal delay buffers in the fast paths to slow these down sufficiently that such race conditions will not arise and short path errors will not be induced. However, the circuit area and power overhead associated with inserting such buffer delays deliberately to slow signal propagation can be significant.
Another problem associated with some implementations of the Razor techniques is that of using the clock signal to define the speculation period. The boundaries of the speculation period need to be signaled to the many different points within the integrated circuit which have employed speculative sampling in circumstances where the path delay concerned gives rise to a significant probability that the speculative value will be incorrect. Using one phase of the clock period to define this speculation period has the advantage that separate speculation defining signals do not have to be widely routed through the integrated circuit. However, controlling the length of the phase being used to indicate the speculation period throughout the integrated circuit in a manner which reliability and consistently defines the speculation period such that errors will be detected and false positives not occur, whilst also taking into account the inevitable variations resulting from process variation within the integrated circuit, represents a significant practical difficulty.